]> www.infradead.org Git - users/jedix/linux-maple.git/commit
clk: vc5: Abort clock configuration without upstream clock
authorMarek Vasut <marek.vasut@gmail.com>
Sat, 15 Dec 2018 00:55:19 +0000 (01:55 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 5 Mar 2019 16:57:58 +0000 (17:57 +0100)
commitffc6b61f38a7165e488de0dba1ffd46f676cc0f7
treeaa21a0cea9971554384758d5cac852dff7774261
parentc70c6e7f3a41a416a82faddf4f3cfd6c19d48fce
clk: vc5: Abort clock configuration without upstream clock

[ Upstream commit 2137a109a5e39c2bdccfffe65230ed3fadbaac0e ]

In case the upstream clock are not set, which can happen in case the
VC5 has no valid upstream clock, the $src variable is used uninited
by regmap_update_bits(). Check for this condition and return -EINVAL
in such case.

Note that in case the VC5 has no valid upstream clock, the VC5 can
not operate correctly. That is a hardware property of the VC5. The
internal oscilator present in some VC5 models is also considered
upstream clock.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Firago <alexey_firago@mentor.com>
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-renesas-soc@vger.kernel.org
[sboyd@kernel.org: Added comment about probe preventing this from
happening in the first place]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/clk-versaclock5.c