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igb: Clear EICR bits for delayed MSI-X interrupts
authorAkihiko Odaki <akihiko.odaki@daynix.com>
Tue, 23 May 2023 02:43:18 +0000 (11:43 +0900)
committerJason Wang <jasowang@redhat.com>
Tue, 23 May 2023 07:20:15 +0000 (15:20 +0800)
commitfe619f2005b15b14f718c56a57152c5c1c06b4c8
treeb70f22126f948edd5ad94ae07948ca2c65d85e2dtree
parent882e54da90a7634d6ccd6d451e2f6950bd68fe04commit | diff
igb: Clear EICR bits for delayed MSI-X interrupts

Section 7.3.4.1 says:
> When auto-clear is enabled for an interrupt cause, the EICR bit is
> set when a cause event mapped to this vector occurs. When the EITR
> Counter reaches zero, the MSI-X message is sent on PCIe. Then the
> EICR bit is cleared and enabled to be set by a new cause event

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
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