]> www.infradead.org Git - users/jedix/linux-maple.git/commit
clk: renesas: rzv2h: Add support for RZ/V2N SoC
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Mon, 7 Apr 2025 19:16:24 +0000 (20:16 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 14 Apr 2025 08:58:14 +0000 (10:58 +0200)
commitf6462eb04f24447e3f9cc33071bbcb888f521985
tree2d5566645af86dfa701efd32f413fb7b2afaa806
parent019b1a845404a97705726272d8a3ced6e78e592e
clk: renesas: rzv2h: Add support for RZ/V2N SoC

The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC
with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present
only on the RZ/V2H(P) SoC.

Add minimal clock and reset entries required to boot the Renesas
RZ/V2N EVK and binds it with the RZ/V2H CPG family driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407191628.323613-9-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/Kconfig
drivers/clk/renesas/Makefile
drivers/clk/renesas/r9a09g056-cpg.c [new file with mode: 0644]
drivers/clk/renesas/rzv2h-cpg.c
drivers/clk/renesas/rzv2h-cpg.h