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drm/exynos: exynos7_drm_decon: fix ideal_clk by converting it to Hz
authorKaustabh Chakraborty <kauschluss@disroot.org>
Fri, 1 Nov 2024 02:31:10 +0000 (11:31 +0900)
committerInki Dae <inki.dae@samsung.com>
Mon, 4 Nov 2024 01:50:46 +0000 (10:50 +0900)
commitf3cb045e2603e80a1633883423b2621aad77989d
treef00b1a33aa7307cda0a2c66d0e993c64cf6feba1tree
parentd31bbacf783daf1e71fbe5c68df93550c446bf44commit | diff
drm/exynos: exynos7_drm_decon: fix ideal_clk by converting it to Hz

The clkdiv values are incorrect as ideal_clk is in kHz and the clock
rate of vclk is in Hz. Multiply 1000 to ideal_clk to bring it to Hz.

Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
drivers/gpu/drm/exynos/exynos7_drm_decon.c diff | blob | history
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