]> www.infradead.org Git - users/dwmw2/qemu.git/commit
target/riscv: implement zicfiss instructions
authorDeepak Gupta <debug@rivosinc.com>
Tue, 8 Oct 2024 22:50:06 +0000 (15:50 -0700)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 30 Oct 2024 01:22:08 +0000 (11:22 +1000)
commitf06bfe3dc38cb6d112d17218cceda223725f3fd4
treeb3a5fc65568233df49baf97b5220c86e995cbd30
parentf21b36a022bb23a696058133bc938e4d91b4d4b8
target/riscv: implement zicfiss instructions

zicfiss has following instructions
 - sspopchk: pops a value from shadow stack and compares with x1/x5.
   If they dont match, reports a sw check exception with tval = 3.
 - sspush: pushes value in x1/x5 on shadow stack
 - ssrdp: reads current shadow stack
 - ssamoswap: swaps contents of shadow stack atomically

sspopchk/sspush/ssrdp default to zimop if zimop implemented and SSE=0

If SSE=0, ssamoswap is illegal instruction exception.

This patch implements shadow stack operations for qemu-user and shadow
stack is not protected.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-17-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_bits.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvzicfiss.c.inc [new file with mode: 0644]
target/riscv/translate.c