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clk: renesas: r9a09g011: Add WDT clock and reset entries
authorPhil Edworthy <phil.edworthy@renesas.com>
Wed, 18 May 2022 15:01:05 +0000 (16:01 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 6 Jun 2022 09:13:30 +0000 (11:13 +0200)
commitefded37b426f4e1b7b004b1e9924ff4bf16ec0fd
tree1a858638ed72338738e2b76f0cec18df5579bfcatree
parente55c4481e71de79d0ef566a238332bd346cef6decommit | diff
clk: renesas: r9a09g011: Add WDT clock and reset entries

Add WDT0 clock and reset entries to CPG driver.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220518150105.48167-1-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g011-cpg.c diff | blob | history
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