clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()

clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()

Since readl() returns a u32, the local variable reg can also have the
data type u32. Furthermore, divf and divq are derived from reg and can
also be a u32.

Since do_div() casts the divisor to u32 anyway, changing the data type
of divq to u32 also removes the following Coccinelle/coccicheck warning
reported by do_div.cocci:

  WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead

Compile-tested only.

Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>