]> www.infradead.org Git - users/jedix/linux-maple.git/commit
media: rzg2l-cru: csi2: Skip system clock for RZ/V2H(P) SoC
authorTommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Fri, 11 Apr 2025 17:05:37 +0000 (19:05 +0200)
committerHans Verkuil <hverkuil@xs4all.nl>
Wed, 23 Apr 2025 08:55:53 +0000 (10:55 +0200)
commited472263fcc48f72e32cb494061bf8b8c333891a
tree8dd9597ca057e41ff414b33b3707e16fa598f6f4
parent15cef2dc7d688d5fc4919aa3c5c272931a8cd087
media: rzg2l-cru: csi2: Skip system clock for RZ/V2H(P) SoC

The RZ/V2H(P) SoC does not require a `system` clock for the CSI-2
interface. To accommodate this, introduce a `has_system_clk` bool flag
in the `rzg2l_csi2_info` structure and update the rzg2l_csi2_probe() to
conditionally request the clock only when needed.

This patch is in preparation for adding support for RZ/V2H(P) SoC.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://lore.kernel.org/r/20250411170624.472257-10-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
drivers/media/platform/renesas/rzg2l-cru/rzg2l-csi2.c