sparc/PCI: Keep resource idx order with bridge register number

sparc/PCI: Keep resource idx order with bridge register number

On one system found strang "no compatible bridge window" warning

PCI: Claiming 0000:00:01.0: Resource 14: 0002000100000000..000200010fffffff [10220c]
PCI: Claiming 0000:01:00.0: Resource 1: 0002000100000000..000200010000ffff [100214]
pci 0000:01:00.0: can't claim BAR 1 [mem 0x2000100000000-0x200010000ffff 64bit]: no compatible bridge window

and we already had pref_compat support that add extra pref bit for device
resource.

It turns out that pci_resource_compatible()/pci_up_path_over_pref_mem64()
just check resource with bridge pref mmio register idx 15, and we have put
resource to use mmio register idx 14 during of_scan_pci_bridge()
as the bridge does not mmio resource.

We already fix pci_up_path_over_pref_mem64() to check all bus resources.

And at the same time, this patch will make resource to consistent sequence
like other arch or directly from pci_read_bridge_bases(),
even non-pref mmio is missing, or out of ordering in firmware reporting.

So hold i = 1 for non pref mmio, and i =2 for pref mmio.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Orabug: 21826746

Signed-off-by: Khalid Aziz <khalid.aziz@oracle.com>
(cherry picked from commit fa259d80c3d8c7ea9f9dd1f78f0292913a1ebd7e)