phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3

phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3

Currently driver supports only x4 lane based functionality using tx/rx and
tx2/rx2 pair of register sets. To support 8 lane functionality with PCIe3,
PCIe3 related QMP PHY provides additional programming which are available
as txz and rxz based register set. Hence add txz and rxz based registers
usage and programming sequences.

As soon as software programs the txz and rxz based register set, hardware
shall "broadcast" the same settings to the tx/rx pair of registers for all
the 8 lanes, which saves the effort of software programming them one by
one.

There might be some tx and/or rx registers on some lanes need minor tweaks,
program them after programming the txz and rxz reigster set.

In addition, x1e80100 uses QMP PHY ver 6.30 for PCIe Gen4 x8, hence add
two new header files to reflect the new register offsets.

Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20241017030412.265000-5-quic_qianyu@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>