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net/mlx5: DPLL, Add clock quality level op implementation
authorJiri Pirko <jiri@nvidia.com>
Wed, 30 Oct 2024 08:11:57 +0000 (09:11 +0100)
committerJakub Kicinski <kuba@kernel.org>
Sun, 3 Nov 2024 16:39:07 +0000 (08:39 -0800)
commite2017f27b6f888fb4ebc5c9a6d984bbf2f8b99ff
tree0e2e4e44c21a6e494893e858ad22ebc0b47c0355tree
parenta1afb959add1fad43cb337448c244ed70bac3109commit | diff
net/mlx5: DPLL, Add clock quality level op implementation

Use MSECQ register to query clock quality from firmware. Implement the
dpll op and fill-up the quality level value properly.

Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Jiri Pirko <jiri@nvidia.com>
Link: https://patch.msgid.link/20241030081157.966604-3-jiri@resnulli.us
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/mellanox/mlx5/core/dpll.c diff | blob | history
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