]> www.infradead.org Git - users/dwmw2/linux.git/commit
drm/i915/slpc: Let's fix the PCODE min freq table setup for SLPC
authorRodrigo Vivi <rodrigo.vivi@intel.com>
Wed, 31 Aug 2022 21:45:38 +0000 (17:45 -0400)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 6 Sep 2022 18:51:43 +0000 (14:51 -0400)
commite1cab970574c001d83e59ca8388c474a57a1afb6
treeaf23011ea86c14a2132e5e3caa2685ef3e731f72
parentedca5a2c373db61efa959307c13ed9156b1c14d9
drm/i915/slpc: Let's fix the PCODE min freq table setup for SLPC

We need to inform PCODE of a desired ring frequencies so PCODE update
the memory frequencies to us. rps->min_freq and rps->max_freq are the
frequencies used in that request. However they were unset when SLPC was
enabled and PCODE never updated the memory freq.

v2 (as Suggested by Ashutosh): if SLPC is in use, let's pick the right
   frequencies from the get_ia_constants instead of the fake init of
   rps' min and max.

v3: don't forget the max <= min return

v4: Move all the freq conversion to intel_rps.c. And the max <= min
    check to where it belongs.

v5: (Ashutosh) Fix old comment s/50 HZ/50 MHz and add a doc explaining
    the "raw format"

Fixes: 7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled")
Cc: <stable@vger.kernel.org> # v5.15+
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Tested-by: Sushma Venkatesh Reddy <sushma.venkatesh.reddy@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220831214538.143950-1-rodrigo.vivi@intel.com
(cherry picked from commit 018a7bdbb090b9155a6509a0d1a684db4afaa5b1)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/i915/gt/intel_llc.c
drivers/gpu/drm/i915/gt/intel_rps.c
drivers/gpu/drm/i915/gt/intel_rps.h