]> www.infradead.org Git - users/jedix/linux-maple.git/commit
clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set
authorBarnabás Czémán <barnabas.czeman@mainlining.org>
Sun, 6 Oct 2024 20:51:58 +0000 (22:51 +0200)
committerBjorn Andersson <andersson@kernel.org>
Mon, 14 Oct 2024 23:51:29 +0000 (18:51 -0500)
commite02bfea4d7ef587bb285ad5825da4e1973ac8263
tree575f706076d8cae89d2b1c45e317bb31d43a4617
parentf903663a8dcd6e1656e52856afbf706cc14cbe6d
clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set

Many qcom clock drivers do not have .width set. In that case value of
(p)->width - 1 will be negative which breaks clock tree. Fix this
by checking if width is zero, and pass 3 to GENMASK if that's the case.

Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org>
Tested-by: Christopher Obbard <christopher.obbard@linaro.org>
Link: https://lore.kernel.org/r/20241006-fix-postdiv-mask-v3-1-160354980433@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
drivers/clk/qcom/clk-alpha-pll.c