]> www.infradead.org Git - users/dwmw2/qemu.git/commit
target: riscv: Add Svrsw60t59b extension support
authorAlexandre Ghiti <alexghiti@rivosinc.com>
Wed, 2 Jul 2025 07:28:52 +0000 (07:28 +0000)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 4 Jul 2025 11:09:49 +0000 (21:09 +1000)
commitdc8bffc4eb0a93d3266cea1b17f8848dea5b915c
treed9d5f76856f6e95643d46bce6c873f8eb9f38823
parent5625817e8b77715b18d0ce3bfcc59fb337e387d8
target: riscv: Add Svrsw60t59b extension support

The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59
for software to use.

Reviewed-by: Deepak Gupta <debug@rivosinc.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com>
Message-ID: <20250702-dev-alex-svrsw60b59b_v2-v2-1-504ddf0f8530@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/riscv/riscv-iommu-bits.h
hw/riscv/riscv-iommu.c
target/riscv/cpu.c
target/riscv/cpu_bits.h
target/riscv/cpu_cfg_fields.h.inc
target/riscv/cpu_helper.c
target/riscv/tcg/tcg-cpu.c