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drm/i915/ddi: Set missing TC DP PHY lane stagger delay in DDI_BUF_CTL
authorImre Deak <imre.deak@intel.com>
Fri, 14 Feb 2025 14:19:54 +0000 (16:19 +0200)
committerImre Deak <imre.deak@intel.com>
Fri, 14 Feb 2025 19:39:06 +0000 (21:39 +0200)
commitdc2b12b34fb8070b304a8725c4c4060058bc6ab7
tree371d14b61ee89291d3335f6096a015febaeb6aedtree
parentdcac00e4d6fdddadde1d5147d1f414f467356077commit | diff
drm/i915/ddi: Set missing TC DP PHY lane stagger delay in DDI_BUF_CTL

Add the missing PHY lane stagger delay programming for ICL-ADL
platforms on TypeC DP outputs.

v2: (Jani)
- Clarify code comment about lane stagger programming.
- Robustify macro calls with parens.

Bspec: 7534, 49533
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250214142001.552916-5-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_ddi.c diff | blob | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
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