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clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width
authorJagan Teki <jagan@amarulasolutions.com>
Wed, 31 Oct 2018 18:36:28 +0000 (00:06 +0530)
committerMaxime Ripard <maxime.ripard@bootlin.com>
Mon, 5 Nov 2018 08:41:27 +0000 (09:41 +0100)
commitdb7548934603d9eda12649dff97ea5c29884405d
tree044ef920f1f3751b791e7eabf5e8b823bcb441c1tree
parent859783d1390035e29ba850963bded2b4ffdf43b5commit | diff
clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width

MUX bits for MMC clock register range are 25:24 where 24 is shift
and 2 is width So fix the width number from 3 to 2.

Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
drivers/clk/sunxi-ng/ccu-sun50i-h6.c diff | blob | history
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