target/armv8: Handle modeswitch for aarch32 secure EL3

target/armv8: Handle modeswitch for aarch32 secure EL3

For aarch32 secure EL3
- Change target_el to 3 for SVC/ABT/IRQ/FIQ/UND/SYS for aarch32 secure
EL3
- Do not update SPSR for SYS, behavior is UNPREDICTABLE (ARMv8-A F5.1.121)
- Do not execute DRPS for SYS, behavior is UNPREDICTABLE (ARMv8-A
F5.1.51)

Change-Id: Ic1484665cd53afcccb5c20b152993a3f0407f8a2
Signed-off-by: Kevin Yang <kangyang@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5854
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Plamena Marinova <pmarinova@hilscher.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>