irqchip/armada-370-xp: Allow mapping only per-CPU interrupts

irqchip/armada-370-xp: Allow mapping only per-CPU interrupts

On platforms where MPIC is not the top-level interrupt controller the
driver currently only supports handling of the per-CPU interrupts (the
first 29 interrupts). This is obvious from the code of
mpic_handle_cascade_irq(), which reads only one cause register.

Bound the number of available interrupts in the interrupt domain to 29 for
these platforms.

The corresponding device-trees refer only to per-CPU interrupts via MPIC,
the other interrupts are referred to via GIC.

Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>