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drm/i915: Reoder CHV EU/slice fuse bits
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 11 Feb 2025 23:19:36 +0000 (01:19 +0200)
committerAndi Shyti <andi.shyti@linux.intel.com>
Tue, 4 Mar 2025 14:39:35 +0000 (15:39 +0100)
commitd4ca1a8b334c69c26fb957b3f07f198f3c24adcc
treedb863c12a932c497915fc4e4c8a4aa905f55197ftree
parentdcf9969259616435ef3197d0f8f2f1b0bcfbb1dacommit | diff
drm/i915: Reoder CHV EU/slice fuse bits

We customarily define the bits of a register in big endian
order. Reorder the CHV fuse bits to match.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-9-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/gt/intel_gt_regs.h diff | blob | history
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