sparc64: Remove node restriction from PRIQ MSI assignments

sparc64: Remove node restriction from PRIQ MSI assignments

The current design of PRIQ only allows MSI routing to CPUs within the same
I/O node. At best this prevents certain types of CPU add/removals as well
as various affinity assignments and at worst can result in dropped
interrupts with CPU DR.

This prior design used a per-node hash table with collision chain (and RCU
synchronization) shared among the root complexes. While it would be
possible to support moving these records between the node hash tables this
is needlessly complicated when a single global table could be used instead
assuming the hashing mechanism was modified to limit the potential for
performance degradation through potentially longer collision chains and
more lookups.

The new design for MSI uses the bottom N bits of the device handle as a
hash versus hashing device handle and msidata together as before. This
exploits the existing numbering scheme to result in zero collisions (even
in an exactly sized hash table). If the numbering scheme is changed on a
future system, that system will still be functional though presumably
with some performance loss. The MSI data is then used as an index into a
array as has been done for prior linux sun4v interrupt model support. Given
the very small number of INTX interrupts, their handling remains
essentially unchanged (now uses a single global hash table, versus per I/O
node as before).

MSI Interrupts from Hypervisor data to ISR:

                                     struct pci_pbm_info *pbms[MAX_PBMS];
                                             +-----------+
                                             |           |
  From Hypervisor:                           |           |
                                             +-----------+
  - root complex devhandle  +---/HASH/------>|           |
  - msidata +--+                             |           |-------+
               |                             +-----------+       |
               |                             |           |       |
               |                             |           |       |
               |                             +-----------+       |
               |                             |           |       |
               |                             |           |       |
               |                             +-----------+       |
               |                                                 |
               |           struct pci_pbm_info                   |
               |              +-----------+<---------------------+
               |              |           |
               |              |    PBM    |
               |              |           |
               |              |           |---+
               |              |           |   |
               |              |           |   |
+--------------+              +-----------+   |
|                                             |
| struct priq_irq **msi_priq                  |
|    +-------------+<-------------------------+
|    |             |
|    |             |
+--->+-------------+       struct priq_irq
     |             |-------->+---------+
     |             |         |         |
     +-------------+         |         |
     |             |         +---------+
     |             |         |   irq   | generic_handle_irq(irq)
     +-------------+         +---------+
     |             |
     |             |
     +-------------+

Signed-off-by: Chris Hyser <chris.hyser@oracle.com>
Reviewed-by Thomas Tai <thomas.tai@oracle.com>

Orabug: 25110748
Signed-off-by: Allen Pais <allen.pais@oracle.com>