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qed: Configure cacheline size in HW
authorTomer Tayar <Tomer.Tayar@cavium.com>
Thu, 6 Apr 2017 12:58:30 +0000 (15:58 +0300)
committerChuck Anderson <chuck.anderson@oracle.com>
Wed, 26 Jul 2017 03:46:57 +0000 (20:46 -0700)
commitd420c3381741f78f6b91e8d03ac7286e9e632d7c
tree3a889ed998865af345ad6e264518d28552f63164tree
parenta78f744585967389fa5df9a909ba6aef5956491bcommit | diff
qed: Configure cacheline size in HW

Orabug: 25933053, 26439680

Default HW configuration is optimal for an architecture where cache
line size is 64B.

During chip initialization, properly initialize the cache line size
in HW to avoid possible redundant PCI transactions.

Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Brian Maly <brian.maly@oracle.com>
drivers/net/ethernet/qlogic/qed/qed_dev.c diff | blob | history
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h diff | blob | history
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