]> www.infradead.org Git - users/jedix/linux-maple.git/commit
drm/i915/dp: Ensure hactive is divisible by slice count
authorAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Wed, 30 Oct 2024 04:10:35 +0000 (09:40 +0530)
committerAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Wed, 6 Nov 2024 11:59:10 +0000 (17:29 +0530)
commitd1f34623ad18524af3c54f92c3baaa4af1d7b3fd
tree783d9204cd66fcf671969672e3c21e84705a8b28
parentb3f5f0c8e9de3fed781bc62dab1ce88183272126
drm/i915/dp: Ensure hactive is divisible by slice count

According to the DSC spec, the slice width should be chosen such that
the picture width (hactive) is evenly divisible by the slice width.
If not, extra pixels (padding) must be added to the last slice to
ensure all slices have the same width.

Currently, we do not support handling these extra pixels.
Therefore, select a slice count that evenly divides the hactive
(slice_width = hactive / slice_count).

This check is already implemented for DSI, where the slice count is
selected from the BIOS.

For DP, currently with 1, 2, 4 slices per pipe it is unlikely to have
slice count not being able to divide hactive, but with 3 DSC engines
and 3 slices, we can have such cases. Adding this check prepares for
future scenarios where such configurations might be used.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-7-ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_dp.c