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clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type
authorGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 22 Jul 2024 11:50:33 +0000 (13:50 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 30 Jul 2024 08:44:18 +0000 (10:44 +0200)
commitccdf745bd10f0682bfd87ba5612fabdf57ff1d5b
tree7ff5161de63c2f254a26f9ab8352cb0763e5e653tree
parent2cf316b4c54e8411c91a901a11a3d78db7fd10b7commit | diff
clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type

The variable PLL2 clock type was superseded by the more generic
variable fractional 8.25 PLL clock type, and its sole user was converted.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8e5564958002351f29435f63de1304fb3b51a725.1721648548.git.geert+renesas@glider.be
drivers/clk/renesas/rcar-gen4-cpg.c diff | blob | history
drivers/clk/renesas/rcar-gen4-cpg.h diff | blob | history
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