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media: ccs-pll: Support two cycles per pixel on OP domain
authorSakari Ailus <sakari.ailus@linux.intel.com>
Fri, 7 Aug 2020 09:00:59 +0000 (11:00 +0200)
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Mon, 7 Dec 2020 14:57:07 +0000 (15:57 +0100)
commitc4c0b222720d413cc866275a0200019eb3c58f33
tree9b3469ff28633d2ef2fcdd1df09ba8794e18ba51tree
parent4e1e8d240dff96bd8dd2c00c5fcd7f04088ace3ccommit | diff
media: ccs-pll: Support two cycles per pixel on OP domain

The l parameter defines the number of clock cycles to process a single
pixel per OP lane. It is calculated based on a new register
op_bits_per_lane.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
drivers/media/i2c/ccs-pll.c diff | blob | history
drivers/media/i2c/ccs-pll.h diff | blob | history
drivers/media/i2c/ccs/ccs-core.c diff | blob | history
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