]> www.infradead.org Git - users/jedix/linux-maple.git/commit
x86/speculation/mds: Add BUG_MSBDS_ONLY
authorThomas Gleixner <tglx@linutronix.de>
Thu, 28 Mar 2019 17:57:15 +0000 (13:57 -0400)
committerMihai Carabas <mihai.carabas@oracle.com>
Mon, 22 Apr 2019 18:16:17 +0000 (21:16 +0300)
commitc26d0c4a4a9ce53fe401f6ef0bb4661639fd459c
tree228e6c44f335e641ce45d06a657e63282e8ef6ea
parentb639ac0d50f1f28f63410c7ba2376913e36e1d8e
x86/speculation/mds: Add BUG_MSBDS_ONLY

commit e261f209c3666e842fd645a1e31f001c3a26def9 upstream

This bug bit is set on CPUs which are only affected by Microarchitectural
Store Buffer Data Sampling (MSBDS) and not by any other MDS variant.

This is important because the Store Buffers are partitioned between
Hyper-Threads so cross thread forwarding is not possible. But if a thread
enters or exits a sleep state the store buffer is repartitioned which can
expose data from one thread to the other. This transition can be mitigated.

That means that for CPUs which are only affected by MSBDS SMT can be
enabled, if the CPU is not affected by other SMT sensitive vulnerabilities,
e.g. L1TF. The XEON PHI variants fall into that category. Also the
Silvermont/Airmont ATOMs, but for them it's not really relevant as they do
not support SMT, but mark them for completeness sake.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Frederic Weisbecker <frederic@kernel.org>
Reviewed-by: Jon Masters <jcm@redhat.com>
Tested-by: Jon Masters <jcm@redhat.com>
(cherry picked from commit 24a8b2c167461f94542ecce1b0e48b30a9ef1a3b)

Orabug: 29526900
CVE: CVE-2018-12126
CVE: CVE-2018-12130
CVE: CVE-2018-12127

Signed-off-by: Kanth Ghatraju <kanth.ghatraju@oracle.com>
Reviewed-by: Mihai Carabas <mihai.carabas@oracle.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
arch/x86/include/asm/cpufeature.h
arch/x86/kernel/cpu/common.c