]> www.infradead.org Git - linux-platform-drivers-x86.git/commit
drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid
authorRohit Khaire <rohit.khaire@amd.com>
Fri, 4 Jun 2021 15:02:56 +0000 (11:02 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 8 Jun 2021 18:03:55 +0000 (14:03 -0400)
commitc247c021b13a2ce40dd9ed06f1e18044dcaefd37
tree20df74a67b30a58b93d950f2bce2b4e4c67e69a4
parentb71a52f44725a3efab9591621c9dd5f8f9f1b522
drm/amdgpu: Fix incorrect register offsets for Sienna Cichlid

RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different
offsets for Sienna Cichlid

Signed-off-by: Rohit Khaire <rohit.khaire@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c