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clk: meson: s4: fix fixed_pll_dco clock
authorXianwei Zhao <xianwei.zhao@amlogic.com>
Mon, 3 Jun 2024 10:04:33 +0000 (18:04 +0800)
committerJerome Brunet <jbrunet@baylibre.com>
Mon, 3 Jun 2024 10:29:37 +0000 (12:29 +0200)
commitc1380adf2e8680a00dedaf1b25c19beadbbe5bbd
treeb3b703ee6b9d906bee4c34924852e88ac4b3f586tree
parent1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0commit | diff
clk: meson: s4: fix fixed_pll_dco clock

The fixed_pll_dco output frequency is not accurate,
add frac factor for fixed_pll_dco clk to fix it.

Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller")
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240603-s4_fixedpll-v1-1-2b2a98630841@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
drivers/clk/meson/s4-pll.c diff | blob | history
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