]> www.infradead.org Git - users/jedix/linux-maple.git/commit
RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED
authorJesse Taube <jesse@rivosinc.com>
Thu, 17 Oct 2024 19:00:20 +0000 (12:00 -0700)
committerPalmer Dabbelt <palmer@rivosinc.com>
Fri, 18 Oct 2024 19:38:32 +0000 (12:38 -0700)
commitc05a62c92516d7679c819f8a5177cf84c8668954
tree468c6a925e7050466ecb177361db878c47073e1a
parent9c528b5f7927b857b40f3c46afbc869827af3c94
RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED

Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED to allow
for the addition of RISCV_VECTOR_MISALIGNED in a later patch.

Signed-off-by: Jesse Taube <jesse@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Reviewed-by: Evan Green <evan@rivosinc.com>
Link: https://lore.kernel.org/r/20241017-jesse_unaligned_vector-v10-3-5b33500160f8@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/Kconfig
arch/riscv/include/asm/cpufeature.h
arch/riscv/include/asm/entry-common.h
arch/riscv/kernel/Makefile
arch/riscv/kernel/fpu.S