dt-bindings: i2c: snps,designware-i2c: declare bus capacitance and clk freq optimized

dt-bindings: i2c: snps,designware-i2c: declare bus capacitance and clk freq optimized

Since there are no registers controlling the hardware parameters
IC_CAP_LOADING and IC_CLK_FREQ_OPTIMIZATION, their values can only be
declared in the device tree.

snps,bus-capacitance-pf indicates the bus capacitance in picofarads (pF).
It affects the high and low pulse width of SCL line in high speed mode.
The legal values for this property are 100 and 400 only, and default
value is 100. This property corresponds to IC_CAP_LOADING.

snps,clk-freq-optimized indicates whether the hardware reduce its
internal clock frequency by reducing the internal latency required to
generate the high period and low period of SCL line. This property
corresponds to IC_CLK_FREQ_OPTIMIZATION.

The driver can calculate the high period count and low period count of
SCL line for high speed mode based on these two properties.

Signed-off-by: Michael Wu <michael.wu@kneron.us>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>