]> www.infradead.org Git - users/willy/xarray.git/commit
riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb
authorClément Léger <cleger@rivosinc.com>
Wed, 19 Jun 2024 11:35:18 +0000 (13:35 +0200)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 26 Jun 2024 14:54:52 +0000 (07:54 -0700)
commitba4cd855839daa2e13f251b2e9db28e5b03b5f40
treeec259266c8af32b0ef24a94c69c0c6e32d478173
parent625034abd52a8c88e829be24c5624eba903a655a
riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb

The Zc* standard extension for code reduction introduces new extensions.
This patch adds support for Zca, Zcf, Zcd and Zcb. Zce, Zcmt and Zcmp
are left out of this patch since they are targeting microcontrollers/
embedded CPUs instead of application processors.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240619113529.676940-9-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/hwcap.h
arch/riscv/kernel/cpufeature.c