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ASoC: cs42l42: Add PLL configuration for 44.1kHz/16-bit
authorRichard Fitzgerald <rf@opensource.cirrus.com>
Thu, 5 Aug 2021 16:11:08 +0000 (17:11 +0100)
committerMark Brown <broonie@kernel.org>
Thu, 5 Aug 2021 22:33:43 +0000 (23:33 +0100)
commitb962bae81fa40fcce7662edcb1e426fa37d32abb
tree56e50452af6891fd9f60599ba2a400f4d89a0162tree
parente5ada3f6787a4d6234adc6f2f3ae35c6d5b71ba0commit | diff
ASoC: cs42l42: Add PLL configuration for 44.1kHz/16-bit

44.1kHz 16-bit standard I2S gives a SCLK of 1.4112 MHz. Add
a PLL configuration for this.

Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210805161111.10410-5-rf@opensource.cirrus.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/codecs/cs42l42.c diff | blob | history
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