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clk: renesas: r9a09g057: Add clock and reset entries for GE3D
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Sun, 9 Mar 2025 21:14:02 +0000 (21:14 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 8 Apr 2025 08:16:09 +0000 (10:16 +0200)
commitb6f2c6bd4e9ea47afa2b66c0c64c296a1fbf4489
treee0d358850ecf18bb965bc035cac5ec22a92adbcftree
parent360387a8f17d2cf7afd894c318df959112f377c7commit | diff
clk: renesas: r9a09g057: Add clock and reset entries for GE3D

Add PLLGPU along with the necessary clock and reset entries for GE3D.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250309211402.80886-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g057-cpg.c diff | blob | history
drivers/clk/renesas/rzv2h-cpg.h diff | blob | history
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