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drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine
authorAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Wed, 30 Oct 2024 04:10:34 +0000 (09:40 +0530)
committerAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Wed, 6 Nov 2024 11:59:09 +0000 (17:29 +0530)
commitb3f5f0c8e9de3fed781bc62dab1ce88183272126
tree2847110b77f241b3f39fdc44d33765732a2402a8tree
parent3013e2e409b75544351998a08c96899412d8f92dcommit | diff
drm/i915/vdsc: Add support for read/write PPS for 3rd DSC engine

With BMG each pipe has 3 DSC engines, so add bits to read/write the PPS
registers for the 3rd DSC engine

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241030041036.1238006-6-ankit.k.nautiyal@intel.com
drivers/gpu/drm/i915/display/intel_vdsc.c diff | blob | history
drivers/gpu/drm/i915/display/intel_vdsc_regs.h diff | blob | history
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