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clk: sunxi: A31: Fix wrong AHB gate number
authorAndre Przywara <andre.przywara@arm.com>
Wed, 23 Jan 2019 00:59:11 +0000 (00:59 +0000)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 23 Mar 2019 13:35:13 +0000 (14:35 +0100)
commitb2a1c6c349816c169ace687aedc5302de2ea5217
tree58a003787b710f70e7045113b27b250e143664dbtree
parenta9652f7280f482e0b02196e5e2edd5a62ce397f1commit | diff
clk: sunxi: A31: Fix wrong AHB gate number

[ Upstream commit ee0b27a3a4da0b0ed2318aa092f8856896e9450b ]

According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.

Fix the gate bit definitions in the clock driver.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/sunxi-ng/ccu-sun6i-a31.c diff | blob | history
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