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dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings
authorBiju Das <biju.das.jz@bp.renesas.com>
Tue, 20 Sep 2022 10:54:59 +0000 (11:54 +0100)
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Wed, 9 Nov 2022 14:45:34 +0000 (16:45 +0200)
commitb1a90f510230afa9483e38fccbf9e4274c92aa8c
tree117ed63e7954f4d3268d217bb8fa2e5b14abe14ftree
parent1760eb547276299ab0c6a6cd3d29469e54ade615commit | diff
dt-bindings: display: bridge: Document RZ/G2L MIPI DSI TX bindings

The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml [new file with mode: 0644] blob
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