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peci: aspeed: Clear clock_divider value before setting it
authorIwona Winiarska <iwona.winiarska@intel.com>
Wed, 17 Apr 2024 13:48:49 +0000 (15:48 +0200)
committerIwona Winiarska <iwona.winiarska@intel.com>
Mon, 17 Jun 2024 13:18:29 +0000 (15:18 +0200)
commitaba59ce109deca2b9abeb9072ddca0ea8682bf5a
tree83a8b6490330b7c5c5ccea40d3fc531caef21058tree
parenta43b9ec091b1b1924ea18883a715e5aadba2543ecommit | diff
peci: aspeed: Clear clock_divider value before setting it

PECI clock divider is programmed on 10:8 bits of PECI Control register.
Before setting a new value, clear bits read from hardware.

Reviewed-by: Billy Tsai <billy_tsai@aspeedtech.com>
Link: https://lore.kernel.org/r/20240417134849.5793-1-iwona.winiarska@intel.com
Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
drivers/peci/controller/peci-aspeed.c diff | blob | history
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