]> www.infradead.org Git - nvme.git/commit
cxl/region: Fix the first aliased address miscalculation
authorLi Ming <ming.li@zohomail.com>
Mon, 17 Mar 2025 07:01:24 +0000 (15:01 +0800)
committerDave Jiang <dave.jiang@intel.com>
Thu, 20 Mar 2025 18:28:45 +0000 (11:28 -0700)
commitaae0594a7053c60b82621136257c8b648c67b512
tree38e5084de7acb73883ce94893c4b4e0de8f9973d
parent3b5d43245f0a56390baaa670e1b6d898772266b3
cxl/region: Fix the first aliased address miscalculation

In extended linear cache(ELC) case, cxl_port_get_spa_cache_alias() helps
to get the aliased address of a SPA, it considers the first address in
CXL memory range is "region start + region cache size + 1", but it
should be "region start + region cache size".

So if a SPA is equal to "region start + region cache size", its aliased
address should be "SPA - region cache size".

Signed-off-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20250317070124.815028-1-ming.li@zohomail.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
drivers/cxl/core/region.c