]> www.infradead.org Git - users/jedix/linux-maple.git/commit
net/mlx5: HWS, Fix pool size optimization
authorVlad Dogaru <vdogaru@nvidia.com>
Thu, 10 Apr 2025 19:17:37 +0000 (22:17 +0300)
committerJakub Kicinski <kuba@kernel.org>
Tue, 15 Apr 2025 00:29:16 +0000 (17:29 -0700)
commita68334f9750f41fc36990840090ef9dbee1e2c7e
treecb70f337ed4387874fd9d9d0d371934ababe2b5c
parent04562694766514f00e7086d3d4884db5f3a22d4e
net/mlx5: HWS, Fix pool size optimization

The optimization to create a size-one STE range for the unused direction
was broken. The hardware prevents us from creating RTCs over unallocated
STE space, so the only reason this has worked so far is because the
optimization was never used.

Signed-off-by: Vlad Dogaru <vdogaru@nvidia.com>
Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Mark Bloch <mbloch@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Link: https://patch.msgid.link/1744312662-356571-8-git-send-email-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c