]> www.infradead.org Git - users/dwmw2/qemu.git/commit
target/riscv: Support Zama16b extension
authorLIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Tue, 9 Jul 2024 11:36:46 +0000 (19:36 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 18 Jul 2024 02:00:42 +0000 (12:00 +1000)
commita60ce58fd971bdcbec6ba96ce989fd399ca1f2d7
tree1de1aba0d2ab96af001012396d001f1525d9f385
parent67e98ebad063e8b028466a754578dd8386aaa5f6
target/riscv: Support Zama16b extension

Zama16b is the property that misaligned load/stores/atomics within
a naturally aligned 16-byte region are atomic.

According to the specification, Zama16b applies only to AMOs, loads
and stores defined in the base ISAs, and loads and stores of no more
than XLEN bits defined in the F, D, and Q extensions. Thus it should
not apply to zacas or RVC instructions.

For an instruction in that set, if all accessed bytes lie within 16B granule,
the instruction will not raise an exception for reasons of address alignment,
and the instruction will give rise to only one memory operation for the
purposes of RVWMO—i.e., it will execute atomically.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240709113652.1239-6-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu_cfg.h
target/riscv/insn_trans/trans_rva.c.inc
target/riscv/insn_trans/trans_rvd.c.inc
target/riscv/insn_trans/trans_rvf.c.inc
target/riscv/insn_trans/trans_rvi.c.inc