]> www.infradead.org Git - users/jedix/linux-maple.git/commit
drm/msm/a5xx: workaround early ring-buffer emptiness check
authorVladimir Lypak <vladimir.lypak@gmail.com>
Sun, 1 Sep 2024 13:54:03 +0000 (13:54 +0000)
committerRob Clark <robdclark@chromium.org>
Sun, 1 Sep 2024 15:17:53 +0000 (08:17 -0700)
commita30f9f65b5ac82d4390548c32ed9c7f05de7ddf5
tree23e91a0828b16e87914ab809b2d1d5e2c5af60b6
parentce050f307ad93bcc5958d0dd35fc276fd394d274
drm/msm/a5xx: workaround early ring-buffer emptiness check

There is another cause for soft lock-up of GPU in empty ring-buffer:
race between GPU executing last commands and CPU checking ring for
emptiness. On GPU side IRQ for retire is triggered by CACHE_FLUSH_TS
event and RPTR shadow (which is used to check ring emptiness) is updated
a bit later from CP_CONTEXT_SWITCH_YIELD. Thus if GPU is executing its
last commands slow enough or we check that ring too fast we will miss a
chance to trigger switch to lower priority ring because current ring isn't
empty just yet. This can escalate to lock-up situation described in
previous patch.
To work-around this issue we keep track of last submit sequence number
for each ring and compare it with one written to memptrs from GPU during
execution of CACHE_FLUSH_TS event.

Fixes: b1fc2839d2f9 ("drm/msm: Implement preemption for A5XX targets")
Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/612047/
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
drivers/gpu/drm/msm/adreno/a5xx_gpu.h
drivers/gpu/drm/msm/adreno/a5xx_preempt.c