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MAINTAINERS: Add pin control and GPIO to the Intel MID record
authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Tue, 4 Feb 2025 17:01:00 +0000 (19:01 +0200)
committerAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Wed, 5 Feb 2025 07:59:13 +0000 (09:59 +0200)
commita1e062ab4a1f19bb0e94093ef90ab9a74f1f7744
tree7c7e8017aa2a370c8048ecc47c3fca05901ef0bctree
parent112f5e0917cff2af35ada29e7db0b4d05bca7941commit | diff
MAINTAINERS: Add pin control and GPIO to the Intel MID record

Intel MID record is not listed all related files. Add to there
pin control and GPIO drivers along with HSU (High Speed UART)
and HSU DMA.

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
MAINTAINERS diff | blob | history
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