]> www.infradead.org Git - users/jedix/linux-maple.git/commit
Merge tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel...
authorArnd Bergmann <arnd@arndb.de>
Tue, 9 Jul 2024 08:53:48 +0000 (10:53 +0200)
committerArnd Bergmann <arnd@arndb.de>
Tue, 9 Jul 2024 08:53:48 +0000 (10:53 +0200)
commit9e6b81559330f3c5fa1a5352af7e9682efe1f7df
treeb612cf81a19821b28ddc3bef7a346ba9f2ab51a9
parenta4dd55f8c2c06e2741a74e49b95b6db0a772e345
parent3d41249c1dee0fa22ebd8d27aa0a280edf943a0e
Merge tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers

RISC-V cache drivers for v6.11

StarFive:
A new driver for the cache controller on the jh8100, which didn't
implement Zicbom and thus needs an implementation of non-standard cache
management operations.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  MAINTAINERS: add microchip soc binding directory to microchip soc driver entry
  MAINTAINERS: add cache binding directory to cache driver entry
  cache: Add StarFive StarLink cache management
  dt-bindings: cache: Add docs for StarFive Starlink cache controller

Link: https://lore.kernel.org/r/20240707-whoever-undesired-c5f6e96ae403@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
MAINTAINERS