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drm/amd/display: Fix 3dlut size for Fastloading on DCN401
authorAdam Nelson <adnelson@amd.com>
Tue, 9 Apr 2024 21:38:44 +0000 (17:38 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 13 May 2024 19:46:27 +0000 (15:46 -0400)
commit9de99fa8c1eab5d7d1f363dcba0786a9b9cc51f4
tree4ad2c7714c2140cae285f4fb72bac87c35973e80tree
parent3ecb039847dcc3d8d683c8aec94e0901dfff518acommit | diff
drm/amd/display: Fix 3dlut size for Fastloading on DCN401

[WHY]
After a non-3dlut test the MPCC_MCM_3DLUT_MODE::MPCC_MCM_3DLUT_SIZE is
incorrect.

[HOW]
Add register write to make valid.

Acked-by: Alex Hung <alex.hung@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Adam Nelson <adnelson@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn401/dcn401_mpc.h diff | blob | history
drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c diff | blob | history
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h diff | blob | history
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