]> www.infradead.org Git - users/willy/xarray.git/commit
dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC
authorBiju Das <biju.das.jz@bp.renesas.com>
Mon, 24 Feb 2025 13:11:17 +0000 (13:11 +0000)
committerThomas Gleixner <tglx@linutronix.de>
Wed, 26 Feb 2025 10:59:49 +0000 (11:59 +0100)
commit9d245214b683e9e4fe2d5c588691337b22c48841
tree56015454229b3ea6c9eb62c3ca086d8ef1f3348f
parent0edaa4593efe9377b4536211f9bc3812e3e53315
dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC

Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E
SoC is almost identical to the one found on the RZ/V2H SoC, with the
following differences:
 - The TINT register base offset is 0x800 instead of zero.
 - The number of supported GPIO interrupts for TINT selection is 141
   instead of 86.
 - The pin index and TINT selection index are not in the 1:1 map
 - The number of TSSR registers is 16 instead of 8
 - Each TSSR register can program 2 TINTs instead of 4 TINTs

Hence add the new compatible string "renesas,r9a09g047-icu" for RZ/G3E SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/all/20250224131253.134199-2-biju.das.jz@bp.renesas.com
Documentation/devicetree/bindings/interrupt-controller/renesas,rzv2h-icu.yaml