]> www.infradead.org Git - users/dwmw2/qemu.git/commit
target/riscv: Correct SXL return value for RV32 in RV64 QEMU
authorTANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Thu, 19 Sep 2024 05:50:43 +0000 (13:50 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 30 Oct 2024 01:22:07 +0000 (11:22 +1000)
commit929e4277c128772bad41cc795995f754cb9991af
tree72e8e960056f5d94f3e1ee5fc0a756be8cb0d2d1
parentefd29e3398001c764fc9f0066ba1589e6ebc1043
target/riscv: Correct SXL return value for RV32 in RV64 QEMU

Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.

Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240919055048.562-4-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h