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csky: Fixup barrier design
authorGuo Ren <guoren@linux.alibaba.com>
Sun, 20 Dec 2020 03:39:27 +0000 (03:39 +0000)
committerGuo Ren <guoren@linux.alibaba.com>
Tue, 12 Jan 2021 01:52:40 +0000 (09:52 +0800)
commit8d11f21a73e662fa11f39447de629cd8caa485c9
tree5aa937f17bd6579d02cb046c34f812b1e41e5a18tree
parentf92ddfb7b5415536e4fe4c7a4868737954159374commit | diff
csky: Fixup barrier design

Remove shareable bit for ordering barrier, just keep ordering
in current hart is enough for SMP. Using three continuous
sync.is as PTW barrier to prevent speculative PTW in 860
microarchitecture.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
arch/csky/include/asm/barrier.h diff | blob | history
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