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cxl: Add extended linear cache address alias emission for cxl events
authorDave Jiang <dave.jiang@intel.com>
Wed, 26 Feb 2025 16:21:20 +0000 (09:21 -0700)
committerDave Jiang <dave.jiang@intel.com>
Wed, 26 Feb 2025 21:07:52 +0000 (14:07 -0700)
commit8c520c5f1e767ed6b47feefca1ed32a097e9b707
tree18140b27a23d73b2634d4e4d1143be64ad4fc31etree
parent0ec9849b63338da7883440ed3f52757cd8c847b1commit | diff
cxl: Add extended linear cache address alias emission for cxl events

Add the aliased address of extended linear cache when emitting event
trace for poison, DRAM and general media of CXL events.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250226162224.3633792-4-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
drivers/cxl/core/mbox.c diff | blob | history
drivers/cxl/core/region.c diff | blob | history
drivers/cxl/core/trace.h diff | blob | history
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