]> www.infradead.org Git - users/jedix/linux-maple.git/commit
perf, riscv: Wire up perf trace support for RISC-V
authorBjörn Töpel <bjorn@rivosinc.com>
Thu, 24 Oct 2024 19:03:51 +0000 (12:03 -0700)
committerNamhyung Kim <namhyung@kernel.org>
Thu, 31 Oct 2024 06:39:34 +0000 (23:39 -0700)
commit8c0d1202bad3aa6e40fb078dc08158f0bb4e03e2
treefdeda0ab1775eb24c4ee6b8717cb93fd46b39344
parent54afc56db221c831479dd1b59eb0657c078355d1
perf, riscv: Wire up perf trace support for RISC-V

RISC-V does not currently support perf trace, since the system call
table is not generated.

Perform the copy/paste exercise, wiring up RISC-V system call table
generation.

Signed-off-by: Björn Töpel <bjorn@rivosinc.com>
Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-riscv@lists.infradead.org
Cc: Atish Patra <atishp@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Link: https://lore.kernel.org/r/20241024190353.46737-1-bjorn@kernel.org
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
tools/perf/Makefile.config
tools/perf/arch/riscv/Makefile
tools/perf/arch/riscv/entry/syscalls/mksyscalltbl [new file with mode: 0755]
tools/perf/util/syscalltbl.c