]> www.infradead.org Git - users/jedix/linux-maple.git/commit
perf/x86/intel, x86/cpu: Simplify Intel PMU initialization
authorSohil Mehta <sohil.mehta@intel.com>
Tue, 18 Mar 2025 22:38:27 +0000 (22:38 +0000)
committerIngo Molnar <mingo@kernel.org>
Wed, 19 Mar 2025 20:34:09 +0000 (21:34 +0100)
commit8b70c7436f51ac0f4702b466e1d9db938944e641
tree7e711b59775aeb9628feefbb0b7b3533248f9ead
parent24a295e4ef1ca8e97d8b7015e1887b6e83e1c8be
perf/x86/intel, x86/cpu: Simplify Intel PMU initialization

Architectural Perfmon was introduced on the Family 6 "Core" processors
starting with Yonah. Processors before Yonah need their own customized
PMU initialization.

p6_pmu_init() is expected to provide that initialization for early
Family 6 processors. But, currently, it could get called for any Family
6 processor if the architectural perfmon feature is disabled on that
processor. To simplify, restrict the P6 PMU initialization to early
Family 6 processors that do not have architectural perfmon support and
truly need the special handling.

As a result, the "unsupported" console print becomes practically
unreachable because all the released P6 processors are covered by the
switch cases. Move the console print to a common location where it can
cover all modern processors (including Family >15) that may not have
architectural perfmon support enumerated.

Also, use this opportunity to get rid of the unnecessary switch cases in
P6 initialization. Only the Pentium Pro processor needs a quirk, and the
rest of the processors do not need any special handling. The gaps in the
case numbers are only due to no processor with those model numbers being
released.

Use decimal numbers to represent Intel Family numbers. Also, convert one
of the last few Intel x86_model comparisons to a VFM-based one.

Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20250318223828.2945651-2-sohil.mehta@intel.com
arch/x86/events/intel/core.c
arch/x86/events/intel/p6.c