]> www.infradead.org Git - users/jedix/linux-maple.git/commit
drm/amd/display: Add early 8b/10b channel equalization test pattern sequence
authorMichael Strauss <michael.strauss@amd.com>
Mon, 4 Dec 2023 08:30:39 +0000 (16:30 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 13 May 2025 13:31:21 +0000 (09:31 -0400)
commit8989cb919b27cd0d2aadb7f1d144cedbb12e6fca
tree8078eda29a0a171a4743bc96e63bec5041c15696
parent90af999835130c506e7e58482474bef3414dd9fa
drm/amd/display: Add early 8b/10b channel equalization test pattern sequence

[WHY]
Early EQ pattern sequence is required for some LTTPR + old dongle
combinations.

[HOW]
If DP_EARLY_8B10B_TPS2 chip cap is set, this new sequence programs phy
to output TPS2 before initiating link training and writes TPS1 to
LTTPR training pattern register as instructed by vendor.

Add function to get embedded LTTPR target address offset.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: TungYu Lu <tungyu.lu@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
drivers/gpu/drm/amd/display/include/link_service_types.h